The eSPI LPC Bridge IIP Core is a full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The eSPI LPC Bridge IIP can be implemented in any technology.

The eSPI LPC Bridge IIP core supports the eSPI LPC bridge protocol standard. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.

The eSPI LPC Bridge IIP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The eSPI LPC Bridge IIP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.