The  SAE J1850 Controller IIP Core is a full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The SAE J1850 controller IIP can be implemented in any technology.

The SAE J1850 controller IIP core supports the SAE J1850-2015 standard. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, APB, OCP, AXI, AXI Lite, Avalon, PLB, Wishbone or custom buses.

The SAE J1850 IIP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The SAE J1850 IIP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.