The Ethernet 25G TSN MAC IIP Core is a full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The Ethernet 25G TSN MAC IIP can be implemented in any technology.

The Ethernet 25G TSN MAC IIP core supports the Various Ethernet TSN IEEE standards. It integrates hardware stacks for timing synchronization (IEEE Standard 802.1AS) and traffic shaping (IEEE Standard 802.1Qav and 802.1Qbv), and a low-latency Ethernet MAC. It supports Preemption. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses .

The Ethernet 25G TSN MAC IIP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The Ethernet 25G TSN MAC IIP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.