The HDMI eARC Receiver IIP Core is a full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The HDMI eARC Receiver IIP can be implemented in any technology.

The HDMI eARC Receiver IIP core supports the standard version 2.1 specification. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, APB, AXI, OCP, VCI, Avalon, PLB, Wishbone, Tilelink or custom buses.

The HDMI eARC Receiver IIP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The HDMI eARC Receiver IIP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.